Transistors such as metal oxide semiconductor field effect transistors (MOSFETs) or simply field effect transistors (FETs) or MOS transistors are the core building blocks of the vast majority of semiconductor integrated circuits (ICs). A FET includes source and drain regions between which a current can flow through a channel under the influence of a bias applied to a gate electrode that overlies the channel and that is separated from the channel by a gate dielectric structure. The ICs are usually formed using both P-channel FETs (PMOS transistors or PFETs) and N-channel FETs (NMOS transistors or NFETs) and the IC is then referred to as a complementary MOS or CMOS circuit. Some semiconductor ICs, such as high performance microprocessors, can include millions of FETs. For such ICs, decreasing transistor size and thus increasing transistor density has traditionally been a high priority in the semiconductor manufacturing industry. Transistor performance, however, must be maintained even as the transistor size decreases.
As advanced metal-oxide-semiconductor (MOS) technology continues to scale and move into the deep-sub-micron geometry dimensions, scaling of the gate dielectric structure has been widely explored to minimize inversion thickness (Tinv), i.e., thickness of an inversion layer or inversion channel within the gate dielectric structure, while maintaining operability of the MOSFETs. One technique that has been employed to scale Tinv while maintaining operability of the MOSFETs is to include one or more high-k dielectric layer in the gate dielectric structure in combination with an interfacial oxide layer such as silicon oxide. The high-k dielectric layer enables Tinv to be scale down to about 14 Å without sacrificing reliability of the FETs. As used herein, high dielectric constant or “high k” means having a dielectric constant greater than about 3.9. However, further scaling of Tinv often results in poor reliability of the resulting FETs, with leakage current through the gate dielectric structure increasing exponentially with the decrease in the Tinv. Nitridation of the interfacial oxide layer has also been employed in combination with use of the high-k dielectric layer to provide Tinv scaling without sacrificing reliability of N-type FETs. For example, Tinv of the gate dielectric structure can be effectively scaled by another 2 Å through nitridation of the interfacial oxide layer. However, nitridation of the interfacial oxide layer negatively impacts reliability of P-type FETs, where negative bias temperature instability (NBTI) is a function of nitrogen in the gate dielectric structure. Regrowth of the interfacial oxide layer through annealing in an oxygenated environment may reverse the impact of nitridation on reliability of the P-type FETs. However, interfacial oxide layer regrowth also occurs at locations of the N-type FETs, thereby negating the benefits of nitridation on Tinv scaling for the N-type FETs. Further, annealing in the oxygenated environment may also adversely impact dielectric properties of the high-k dielectric layer.
Accordingly, it is desirable to provide methods of scaling thickness of a gate dielectric structure that enables selective regrowth of the interfacial oxide layer at particular locations of the interfacial oxide layer while also minimizing impact on dielectric properties of the high-k dielectric layer. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.